AS5013-IQFT-1000【PDF 12/32 页】IC ENCODER HALL SENSOR 16-QFN

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www.ams.com/AS5013

Revision 1.11

12 - 32

AS5013

Datasheet - Detailed Description

7.5.4 I睠 Modes

The AS5013 supports the I睠 bus protocol. A device that sends data onto the bus is defined as a transmitter and a device receiving data as a

receiver. The device that controls the message is called a master. The devices that are controlled by the master are referred to as slaves. A

master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions must control the

bus. The AS5013 operates as a slave on the I睠 bus. Connections to the bus are made through the open-drain I/O lines SDA and the input SCL.

Clock stretching is not included.

Automatic Increment of Address Pointer.

The AS5013 slave automatically increments the address pointer after each byte transferred. The increase of the address pointer is independent

from the address being valid or not.

Invalid Addresses.

If the user sets the address pointer to an invalid address, the address byte is not acknowledged. Nevertheless a read or write cycle is possible.

The address pointer is increased after each byte.

Reading.

When reading from a wrong address, the AS5013 slave data returns all zero. The address pointer is increased after each byte. Sequential read

over the whole address range is possible including address overflow.

Writing.

A write to a wrong address is not acknowledged by the AS5013 slave, although the address pointer is increased. When the address pointer

points to a valid address again, a successful write access is acknowledged. Page write over the whole address range is possible including

address overflow.

The following bus protocol has been defined:

n Data transfer may be initiated only when the bus is not busy.

n During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH

are interpreted as start or stop signals.

Accordingly, the following bus conditions have been defined:

rCL1

Rise time of SCLH signal

after repeated START

condition and after an

acknowledge bit

External pull-up

source of 3mA

160

Rise Time of SDA and

SCL Signals

20+0.1C

120

Fall time of SDA and SCL

signals

20+0.1C

120

SU;STO

Setup Time for STOP

Condition

600

160

Noise margin at LOW level

For each connected

device (including

hysteresis)

0.1VDDp

Noise margin at HIGH

level

0.2VDDp

1. For bus line loads C

between 100pF and 400 pF the timing parameters must be linearly interpolated.

2. After this time the first clock is generated.

3. A device must internally provide a minimum hold time (300n for Fast-mode, 80ns / max 150ns for High-speed mode) for the SDA signal

(referred to the VIHmin of the SCL) to bridge the undefined region of the falling edge of SCL.

4. A fast-mode device can be used in standard-mode system, but the requirement t

SU;DAT

= 250ns must then be met. This is automatically

the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL

signal, it must output the next data bit to the SDA line t

Rmax

+ t

SU;DAT

= 1000 + 250 = 1250ns before the SCL line is released.

Symbol

Parameter

Condition

Fast-mode

HS-mode C

=100pF

HS-mode

=400pF

Unit

Min

Max

Min

Max

Min

Max

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